1. Field of the Invention
The present invention is related to a calculation apparatus and an encrypt and decrypt processing apparatus, for executing a plurality of arithmetic processing operations, while matrix calculating operations are employed in at least a portion of these plurality of arithmetic processing operations.
2. Description of the Related Art
The common key cryptosystem “AES (Advanced Encryption Standard)” of US standard is the common key cryptosystem which has been used in the world instead of the conventional common key cryptosystem “DES (DATA Encryption Standard).” The technical specification of AES is disclosed in “FIPS190-2.”
The common key cryptosystem “AES” contains matrix calculating operations referred to as “MixColumns” and “InvMixColumns.” The thesis entitled “Effective Implementation Method of Polynomial Multiplying Circuit in AES”, national conference of Information Processing Institute No. 63 (post period of Heisei-era 13) discloses such a technical idea that both a partial circuit for constituting MixColumns and a partial circuit for constituting InvMixColumns can be shared. As previously explained, because the circuits are shared, the size of the circuits can be made smaller than if the circuits for constituting MixColumns and the circuits for constituting InvMixColumns are independently designed.
Generally speaking, when LSI is designed, two requirements are established, namely, circuit sizes of LSI must be reduced, and LSI must be operated in higher operating frequencies. The reductions of the circuit sizes can reduce costs of LSI, whereas the operations of LSI at the higher operating frequencies can improve performance thereof. In order to decrease circuit sizes of LSI, it can be realized by those portions for performing the same process operations are processed by a shared circuit.
On the other hand, in order to operate LSI in higher operating frequencies, maximum delay paths which may constitute a factor for determining an operating frequency must be made shorter in synchronous type LSI. A maximum delay path is called a critical path, and corresponds to such a signal line which executes the longest calculation operation in a calculating circuit within a cycle of a synchronous signal. An operating frequency of a synchronous type LSI can be increased by shortening this critical path. In order to shorten a critical path, the following circuit arrangement is required. That is, circuit portions capable of calculating in parallel are discovered, and thus, such a circuit capable of executing a parallel calculation must be arranged.
If the previously explained thesis is applied to LSI designing of AES, then a circuit size of designed LSI may be decreased. However, this thesis neither describes, nor teaches such an LSI designing idea that calculations are carried out in a parallel manner so as to realize a high speed calculation, namely, the higher operating frequency cannot be realized.